Most computer systems use volatile memory (VM) (e.g. dynamic random access memory (DRAM) including variations thereof such as SDRAM, and other types of volatile RAM such as volatile SRAM, etc.) for temporarily storing data. Temporarily retained in the volatile memory, data may be lost when power supply to the VM is interrupted. If a computer system suffers from a sudden failure, e.g. a hardware or software crash, there is a risk that temporarily retained data may be permanently lost.
Methods of preserving data in the event of a power interruption have been recognized in the conventional art and various techniques have been developed to provide solutions. For example:
U.S. Pat. No. 5,889,933 discloses a RAID system that has two write modes. In a normal write mode, a host computer receives a write confirmation once an array controller receives data from the host computer. In a safe write mode, however, the array controller copies to non-volatile random access memory (NVRAM) all data received from the host computer for writing to disk drives. The array controller switches from normal write mode to safe write mode upon detection of an AC power failure.
U.S. Pat. No. 8,074,112 discloses a method for memory backup including: detecting a failure in a main power supply that supplies power to a volatile memory that is coupled to a RAID controller, switching to a temporary power supply to supply power to the volatile memory in response to detecting the main power supply failure, and transferring data from the volatile memory to a non-volatile memory coupled to the RAID controller subsequent to switching to the temporary power supply.
European Patent No. 0613077 discloses a method for preserving dirty data, whereby known test information is written to a memory address. A VM reset signal is blocked until the processor accesses the memory address and compares the information stored in the memory address with the known test information. If the comparison fails or the processor cannot access the memory address, it is determined that the reset signal was caused by a power failure and the memory is reset. However, if the comparison succeeds, it is determined that the reset signal was not caused by a power failure and the memory is not reset thereby preserving the memory contents.